1. Technical Field
The present invention relates generally to semiconductor fabrication processes and, more particularly, to a semiconductor fabrication process useful in building a transistor having a raised source-drain structure.
2. Description of Related Art
A transistor having a raised source-drain structure is well known in the art. There are a number of recognized fabrication processes for building such a transistor. These processes share in common a fabrication step for selectively depositing semiconductor material above the source region and drain region of a partially constructed transistor. This selective deposition of semiconductor material to form the raised source-drain structure is commonly accomplished through selective epitaxial growth.
FIG. 1 shows a cross-section of semiconductor structure for a partially constructed MOS-type transistor. The semiconductor structure includes a transistor gate 10 formed above a substrate 12 (for example, a silicon substrate including, if desired, doping). The transistor gate 10 includes, for example, a gate oxide 14, a gate conductor 16, an off-set spacer 18, a liner 20 and a sidewall spacer 22. The substrate 12 includes doped regions 24 on either side of the transistor gate 10 defining the source region and drain region (such regions including, although not specifically illustrated, lightly doped structures, heavily doped structures, extensions and/or halo implants as known in the art). A channel region 26 of the transistor is positioned between the doped regions 24 and underneath the transistor gate 10. Those skilled in the art are well aware of suitable fabrication processes for forming the semiconductor structure with the partially constructed MOS-type transistor shown in FIG. 1.
As a result of the fabrication processes used to reach the partially constructed MOS-type transistor shown in FIG. 1, those skilled in the art recognize that the upper surface 28 of the substrate 12 at the doped regions 24 (comprising the source region and the drain region) can become damaged. For example, this damage could be the result of the performance of one or more plasma etching operations or other fabrication or treatment processes used to define the transistor gate 10. This results in the presence of a damaged surface layer 30 at the upper surface 28 of each of the doped regions 24.
In the context of forming a raised source-drain structure above the doped regions 24, it is important to provide a high quality interface between the doped regions 24 and the overlying raised source-drain structure produced by subsequent epitaxial growth. The damaged surface layer 30 is not considered by those skilled in the art to present an acceptable high quality interface for a raised source-drain structure. Prior art semiconductor transistor fabrication processes accordingly teach placing the semiconductor structure of FIG. 1 in a first process chamber 80 and subjecting the semiconductor structure to a treatment and cleaning process (such as an O2 plasma flash with oxide and H2 cleaning) so as to remove damaged surface layer 30 at each of the doped regions 24. The prior art further teaches using the first process chamber 80 to further subject the semiconductor structure to a reactive ion etch (RIE) so as to remove damaged surface layer 30 at each of the doped regions 24. FIG. 2 shows a cross-section of the semiconductor structure with the partially constructed MOS-type transistor following processing in the first chamber to remove the damaged surface layer 30.
The advantage of performing RIE etching along with the other treatment and cleaning processes (such as an O2 plasma flash with oxide and H2 cleaning), as opposed to solely using the other treatment and cleaning processes, to remove damaged surface layer 30 at each of the doped regions 24, is that the use of the RIE etch process produces a clean interface surface 32 suitable for supporting subsequent epitaxial growth to form the overlying raised source-drain structure. An additional advantage to using the RIE etch process is that the subsequent epitaxial growth to form the overlying raised source-drain structure has a growth rate that is doping independent.
A disadvantage of performing RIE etching (and with respect to the use of other treatment and cleaning processes, as well) to remove damaged surface layer 30 is that a subsequent high temperature pre-bake process is required to prepare the interface surface 32 of the doped regions 24 before beginning epitaxial growth and forming the overlying raised source-drain structure. So, a next step in the prior art fabrication process comprises subjecting the semiconductor structure as shown in FIG. 2 to a pre-bake treatment 82. It is recognized, however, that the pre-bake treatment 82 with a high thermal budget results in a significant diffusion of dopants for the source-drain extensions and halo implants. Thus, it is desired to minimize that the thermal budget preparing the interface surface 32 as much as possible. Nonetheless, the pre-bake operation is typically performed at a relatively high temperature at or exceeding approximately 800° C., and some undesired dopant diffusion will necessarily occur.
Following completion of the pre-bake and preparation of the interface surface 32, a selective epitaxial growth is performed so as to deposit semiconductor material forming the raised source-drain structures 34 over the doped regions 24. It is important to note that the process for selective epitaxial growth from the interface surface 32 is performed in a second process chamber 84 (i.e., a process chamber 84 different from the first process chamber 80 used RIE etching and the removal of damaged surface layer 30). FIG. 3 shows a cross-section of a semiconductor structure with a partially constructed MOS-type transistor following processing in the second chamber 84 to epitaxially grow the raised source-drain structures 34 from the interface surface 32. Then use of RIE etching to remove the damaged surface layer 30 and prepare the interface surface 32 for epitaxial growth is preferred because the resulting semiconductor structure does not exhibit a “seam” (or there is only a minimal seam) or interface at the interface surface 32 between the doped regions 24 and the raised source-drain structures 34.
The higher the thermal budget for the pre-bake, the higher the quality of the clean interface surface 32. However, the higher the thermal budget the greater the undesired degree of dopant diffusion with respect to the source-drain extensions and halo implants. Thus, those skilled in the art using the known prior art processes for fabricating transistors with raised source-drain structures must trade-off the advantage of a clean interface surface 32 against the disadvantage of higher dopant diffusion. For example, a lower temperature cleaning and a lower temperature pre-bake may address issues with respect to excessive undesired dopant diffusion of the source-drain extensions and halo implants, but produce a lower quality interface surface 32 for epitaxial growth of the raised source-drain regions with a distinct “seam” interface exhibiting oxygen and/or carbon concentrations. Conversely, a high temperature pre-bake may produce a cleaner interface surface for satisfactory epitaxial growth of the raised source-drain regions, but produce an unacceptable degree of extension and halo implant dopant diffusion.
There is a need in the art for an improved process for fabricating raised source-drain structures that addresses the foregoing, and other, deficiencies, limitations and trade-offs noted with respect to the prior art processes and fabrication techniques. In particular, there would be an advantage to a process for forming raised source-drain structures with clean interface surfaces using a lower thermal budget that did not produce unacceptable dopant diffusion.